1. Field of the Invention
The present invention relates to a storage device including a flash memory, a computer system using the storage device, and a data writing method and, more specifically, to a speed enhancement technology in the storage device for data transfer.
2. Description of the Related Art
In recent years, flash memories are receiving attention as a storage medium for use for digital still cameras or mobile computer equipment.
The flash memory is a semiconductor memory for storing therein data. For data storage, using electron tunneling or acceleration of hot electrons, electrons are injected to a floating gate or a trapping layer after being made to pass through a gate insulation film so that a threshold value of a cell transistor is changed. In such a semiconductor memory, only one transistor of multilayer gate or MNOS (Metal Nitride Oxide Semiconductor memory) structure can configure a memory cell so that the resulting memory can be inexpensive and large in capacity.
For such a semiconductor memory, a NAND flash memory is typically exemplified.
FIG. 1 is a diagram showing an exemplary internal configuration of a NAND flash memory.
The NAND flash memory of FIG. 1 includes a plurality of memory units 1-1 to 1-n in an array (in length and width directions). The memory units 1-1 to 1-n are connected to bit lines BL1 to BLn, respectively.
For example, a gate of a selection transistor 2 is connected to a selection gate line SL1, and a gate of another selection transistor 3 is connected to a selection gate line SL2. Gates of memory cells N0 to N15 are connected to word lines WL0 to WL15, respectively.
The memory cells N0 to N15 are each of multilayer gate structure, and store therein data in accordance with the amount of charge stored for a floating gate. That is, when a lot of electrons are stored in the floating gate, a transistor is increased in threshold value. For assessment of data, an access circuit 4 including a sense amplifier or others is used to detect whether there is a current flow from the charged bit lines BL1 to BLn to the memory units 1, i.e., 1-1 to 1-n. 
Such a NAND flash memory has no need to include an area for every memory cell to come in contact with the bit lines. In this sense, the NAND flash memory is considered suitable for use as a medium of inexpensive large-capacity storage devices.
The issue here is that the flash memory is generally considerably slow in program speed, and requires several hundreds of μ seconds per cell. With the fact that no overwriting of data is possible, there needs to erase data before running of a program, and this takes several m seconds. To deal with such a problem, many memory cells are subjected to parallel processing.
That is, writing of a memory cell group 5, i.e., page unit, including cells all connected to the word line WL0 is performed collectively all at once, and erasing of a cell block 6 configured by page groups each sharing a memory unit is performed collectively all at once. Through such collective writing and erasing, the program is increased in transfer speed.
More specifically, Non-patent Document 1 (Digest of ISSCC2002, p 106, session 6.4) describes a NAND flash memory of 1 Gb, in which a page size is 2 kbytes, and an erase block size is 128 kB. That is, in a memory array, a memory cell group of 128 kbytes is erased in parallel, and a memory cell is programmed thereto in parallel for every 2 kbytes, thereby realizing the program transfer speed of 10 MB/s.